1. Field of the Invention
The invention relates to memories, and more particularly to testing of memories.
2. Description of the Related Art
Downgrade memories are memory chips with defective memory cells. When a manufacturer produces a batch of memory chips, the manufacturer performs a quality test to verify the quality of the batch of memory chips. If the batch of memory chips cannot fill requirements of the quality test, the memory chips are then marked as downgrade memory chips and sold in a price lower than that of normal memory chips.
Generally, a downgrade memory chip comprises a majority of memory cells capable of normally storing data. Only a portion of memory cells of the downgrade memory cell have defects due to errors in the manufacture process and cannot normally store data. When a data storage device uses a downgrade memory chip to store data, a controller of the data storage device must first scan all the memory cells of the downgrade memory chip to find the locations of the defective memory cells and then record the defective memory cells in a scan result. The controller of the data storage device can then store data in normal memory cells of the downgrade memory chip and avoid storing data in defective memory cells of the downgrade memory chip according to the scan result.
Referring to FIG. 1, a flowchart of a method 100 of testing a memory is shown. A controller can scan memory cells of a downgrade memory according to the method 100 to identify locations of defective memory cells of the downgrade memory. First, the controller sends a write command and a write address in a test range of a memory to the memory (step 102). The controller then sends test data to the memory (step 104). After the memory receives test data, the memory then writes the test data to the write address of the memory according to the write command. The controller then checks whether the test range of the memory has been filled with the test data (step 106). If not, the controller selects a new write address to be sent to the memory from the test range (step 108) and then sequentially sends a new write command, the new write address, and the test data to the memory to direct the memory to write the test data to the new write address (steps 102 and 104). Thus, the test range of the memory is gradually written with the test data.
After the test range of the memory is filled with the test data (step 106), the controller sends a read command and a read address in the test range to the memory (step 110). When the memory receives the read command and the read address, the memory reads data from the read address according to the read command to obtain read-out data, and sends the read-out data to the controller. When the controller receives the read-out data (step 112), the controller compares the read-out data with the test data (step 114). When the read-out data is not identical to the test data, the memory cells corresponding to the read address are identified as defective memory cells, and the controller records the read address as a defective address in the scan result (step 116). When the read-out data is identical to the test data, the memory cells corresponding to the read address are identified as normal memory cells. If the addresses in the test range of the memory have not been completely read (step 118), the controller selects a new read address to be sent to the memory from the test range (step 120), and then sends a new read command and the new read address to the memory. After all addresses in the test range have been read, the controller can identify all defective memory cells in the test range according to the defective addresses recorded in the scan result.
Although the method 100 shown in FIG. 1 can precisely identify defective addresses, the method 100 has shortcomings. Whenever the controller writes test data to the memory, the controller must send test data to the memory. Sending the test data from the controller to the memory requires a data transmission period which causes delay to the entire memory test process. Referring to FIG. 2A, a block diagram of a data storage device 200 is shown. The data storage device 200 comprises a controller 202 and a nonvolatile memory 204. The controller 202 comprises a data buffer 214 storing test data. Whenever the controller 202 writes test data to the nonvolatile memory 204, the controller 202 must send the test data to the nonvolatile memory 204. After the nonvolatile memory 204 receives the test data from the controller 202, the nonvolatile memory 204 then stores the test data in a data register 224, and then writes the test data from the data register 224 to a memory cell with a write address. For example, to write the test data to the memory cell 241, the controller 202 has to send the test data to the nonvolatile memory 204 via the data path 231. To write the test data to the memory cell 242, the controller 202 still has to send the test data again to the nonvolatile memory 204 via the data path 232.
A controller generally sends data of a page to a memory. Because the data amount of a page is huge, transmission of page data from the controller to the memory requires a long period. Referring to FIG. 2B, a schematic diagram of transmission of a write command and a write address from a controller to a memory is shown. The controller first sends a write command 80h to the memory, and then sends a write address to the memory, wherein the write address comprises column addresses CA1 and CA2 and row addresses RA1, RA2, and RA3. Finally, the controller sends test data D1˜DN to the memory. If the test data has a data length of 2 KB, and a byte is transmitted from the controller to the memory in a clock cycle, transmission of the test data requires a total period of 2K clock cycles. If the test data is repeatedly sent to the memory in the memory test process, the memory test process is therefore delayed by a long data transmission period. A method of efficiently writing test data to a memory is therefore required.